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Guild: wafer.space Community
Channel: Information / general / Most if not all of the DRC errors should
After: 09/30/2025 23:59
Before: 11/01/2025 00:00
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[10/06/2025 12:47] mole99



[10/06/2025 12:47] mole99
Nice! I'm currently integrating the KLayout DRC deck into the gf180mcu LibreLane setup. This should catch any additional errors.


[10/06/2025 12:49] mole99
If you can still recall, it would be great if you could let @Tim Edwards know which errors didn't show up in magic DRC.


[10/06/2025 13:11] tholin
CO.6a: Metal1 end-of-line overlap contact


[10/06/2025 13:13] tholin
Example being the version of the aoi22_2 cell at this commit:
https://github.com/AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3/blob/112ea06e961bfe76b10c66805db09410885fccf4/pdk/libs.ref/gf180mcu_as_sc_mcu7t3v3/mag/gf180mcu_as_sc_mcu7t3v3__aoi22_2.mag

{Embed}
https://github.com/AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3/blob/112ea06e961bfe76b10c66805db09410885fccf4/pdk/libs.ref/gf180mcu_as_sc_mcu7t3v3/mag/gf180mcu_as_sc_mcu7t3v3__aoi22_2.mag
gf180mcu_as_sc_mcu7t3v3/pdk/libs.ref/gf180mcu_as_sc_mcu7t3v3/mag/gf...
Custom Standard Cell Library for GF180MCU process node on open PDK. - AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3
2025-10_media/gf180mcu_as_sc_mcu7t3v3-14BFE


[10/06/2025 13:24] rtimothyedwards_19428
As far as I can tell, the rule is implemented correctly in magic, and I don't see any error in that layout.


[10/06/2025 13:26] tholin
I got it after running a flow


[10/06/2025 13:27] rtimothyedwards_19428
But I'm looking at the layout and I don't see an error.  Was there a coordinate shown indicating where the error is (or where it thinks the error is)?


[10/06/2025 13:30] rtimothyedwards_19428
And what tool flagged an error?


[10/06/2025 13:30] tholin
It indeed does not show up if the DRC in run on the cell in isolation.


[10/06/2025 13:30] tholin
I got it after running KLayout DRC on a flow output


[10/06/2025 13:31] rtimothyedwards_19428
I don't get how that's possible, other than a bad implementation in klayout.  How can a minimum overlap be satisified within a cell but violating in a larger context?


[10/06/2025 13:33] mole99
It would definitely be useful to have the flow output in order to reproduce the error.


[10/06/2025 13:41] tholin
Here’s the whole run.

{Attachments}
2025-10_media/latest-63DB3.zip


[10/06/2025 13:42] tholin


{Attachments}
2025-10_media/image-DF2FD.png


[10/06/2025 14:37] rtimothyedwards_19428
@Tholin :  I can't find the error anywhere in the files.  Where should I be looking?


[10/06/2025 14:49] tholin
Currently, you have to run KLayout DRC separately through `python $PDK_ROOT/$PDK/libs.tech/klayout/drc/run_drc.py --variant=D --run_dir=drc --path=runs/latest/final/gds/user_project_example.gds`


[10/06/2025 14:49] tholin
Which is what I’m doing manually after each run.


[10/06/2025 16:04] rtimothyedwards_19428
That might require klayout with ruby support (which I haven't tried to compile yet)?  I get `ERROR: Can't run macro (no interpreter): /home/tim/devel/open_pdks/Tholin/latest/drc/main.drc`.

Can you post the DRC database output from klayout?


[10/06/2025 16:27] tholin


{Attachments}
2025-10_media/user_project_example_main-F4D13.lyrdb


[10/06/2025 17:18] rtimothyedwards_19428
It appears that whether or not this is a rule violation entirely depends on the definition of "end of line".  Since the DRC document does not (as far as I could find) define "end of line", then it remains unknown whether the klayout rule is overly conservative or if the magic rule is not conservative enough.  If the latter, I'm not sure that there is an edge rule in magic that would capture the rule intent.


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